Issues in the Scalability of Gate-level Morphogenetic Evolvable Hardware

Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing circuit and FPGA complexity. To overcome this there have been moves towards encoding a growth process, known as morphogenesis. Using a morphogenetic approach, has shown success in scaling gate-level EHW for a signal routing problem, however, when faced with a evolving a one-bit full adder, unforseen difficulties were encountered. In this paper, we provide a measurement of EHW problem difficulty that takes into account the salient features of the problem, and when combined with a measure of feedback from the fitness function, we are able to estimate whether or not a given EHW problem is likely to be able to be solved successfully by our morphogenetic approach. Using these measurements we are also able to give an indication of the scalability of morphogenesis when applied to EHW.